Digital Design using Verilog

This course focuses on synthesizable design of digital VLSI system using Verilog HDL language. The course consists of three parts. The first part is on the fundamental knowledge of Verilog HDL language. Built on this, the important concept of synthesizable digital design is introduced and discussed in the format of various design cases in the second part. The third part covers topics ranging from commonly used architecture-level optimizing technique to practical design examples in modern digital signal processing systems.

029461